In this experiment you will be exposed to the coding of FSM – Finite State Machines using Verilog. The procedure will use the methods you were exposed to in Digital Logic II which allowed you to derive a circuit containing flip-flops and logic gates, then you will describe the circuit using Verilog. Experiment: Each section will receive a problem description which you will design in the lab by following the steps given below. To facilitate your understanding an example will be

The civil war has been given many names: the war between the states, the war against northern aggression, the second american revolution, the lost cause, the war of the rebellion, the brothers' war, and the late unpleasantness. famous poet walt whitman called it the war of attempted secession. confederate general joseph johnston called it the war against the states. by whatever name, it was unquestionably the most important event in the life of the nation. which name do you feel best fits this war from the list above? maybe you have another name you think would be even better? give the name you feel fits this war best, and in a sentence or two, explain your reasoning.

For each of the following examples of data, determine which scale of measurement is used. a) the number of miles joggers run per week. b) the starting salaries of graduates of mba programs c) the months in which a firm's employees choose to take their vacations. d) the final letter grades received by students in a math course.

What would you call a political system that is only meant to last for a short time