Engineering, 04.04.2020 06:05 falgunim4

Consider a processor and a program that would have an IPC of 1 with a perfect 1-cycle L1 cache (All accesses are hit). Assume that each additional cycle for cache/memory access causes program execution time to increase by one cycle and 50% of instructions are loads/stores and the L1-Instruction cache hit rate is 100%. Assume the following MPKMIs(Miss Per Kilo Memory Instruction) and latencies for the following caches: • L1:32 KB: 1-cycle: 80 MPKMI • L2: 256 KB: 10-cycle: 50 MPKMI • L3:2 MB: 30-cycle: 20 MPKMI • 14:32 MB: 100-cycle: 5 MPKMI. • Memory: 250-cycles Estimate the CPI for the following cache configurations:

1. L1-L2-L3-L4
2. L1-L2-L3
3. L2-L3-L4
4. L1-L2-L4

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Consider a processor and a program that would have an IPC of 1 with a perfect 1-cycle L1 cache (All...