Engineering, 02.04.2020 19:47 jay5134

Design a ROM of size 64X8 bit in VHDL. Your ROM takes as input an address and a clock and output the content of the ROM at the corresponding input address on the rising edge of the clock.

Use your ROM to implement:
a. The combinational circuit of Design problem II above
b. The FSM of Lab 3, problem 3
c. The FSM of Lab 3, problem 4. The ROM should replace the combinational bloc

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Design a ROM of size 64X8 bit in VHDL. Your ROM takes as input an address and a clock and output the...