One challenge for architects is that the design created today will require several years of implementation, verification, and testing before appearing on the market. This means that the architect must project what the technology will be like several years in advance. Sometimes, this is difficult to do.
a: According to the trend in device scaling historically observed by Moore’s law, the number of transistors on a chip in 2028 should be how many times the number in 2018? (You may assume a 40% increase in the number of transistors per year.)
b: The increase in performance once mirrored this trend. Had performance continued to climb at the same rate as in the 1990s, approximately what performance would chips have over the VAX-11/750 in 2028 (assume a 40% increase in performance per year)? You may assume that the speedup in the year 2003 over the VAX-11/750 is 6043x.
c: At the current rate of increase of the mid-2000s (assume 22% per year), what is a more updated projection of performance in 2028? You may assume that the speedup in the year 2010 over the VAX-11/750 is known to be 24,129.
d: What has limited the rate of growth of the clock rate, and what are architects doing with the extra transistors to increase performance?
e: The rate of growth for DRAM capacity has also slowed down. For 20 years, DRAM capacity improved 60% each year. If 8 Gbit DRAM was first available in 2015 and 16 Gbit DRAM was not available until 2019, what is the current DRAM growth rate.