Draw a datapath (yes, only the datapath, not the fsm) of a circuit that adds two n-bit 2's complement binary numbers, a and b, stored in two n-bit right shift registers, ra and rb. each shift register has serial output so and serial input si. beginning with the least significant pair of bits in ra and rb, the circuit should add one pair at a time through a single full‐adder (fa) circuit. the sum bit from the fa output should be stored back into shift register ra. that is, ra will hold the n-bit sum after n shifts.