A byte-addressable memory system contains 4 memory modules each of which is 32 bits wide by 228 cells deep. The system employs a 1 MB 2-way set associative cache with 128-byte cache lines. It also uses a 32-bit CPU-to-memory data bus as well as 32-bit physical addresses. 4 clock cycles are required to complete all of the activity required for a read from a single memory module (one cycle to select the module and send the address, one cycle to decode the address, one cycle to perform the access, and one cycle to transmit the data.) a) Assuming that the memory system employs low order interleaving of cells,
show a diagram of the proper 32-bit physical address format, including the width and position of each field. Also describe how each field is used.
b) Assuming that the memory system employs high order interleaving of cells,
show a diagram for the proper 32-bit physical address format, including the width and position of each field. Also describe how each field is used.
c) What is the minimum number of clock cycles required to fill a cache line if the memory system uses low order interleaving?
d) What is the minimum number of clock cycles required to fill a cache line if the memory system uses high order interleaving?