Assume the elements in the MIPS single-cycle datapath and control have the following delays in picoseconds (ignore the delay time through the Control Unit). Element Parameter Delay (ps)
PC clock-to-Q tpcq_PC 30
Multiplexer tmux 25
ALU TALU 200
Data and Instruction
Memory (read or write) tmem 250
Register file (read
or write) TRF 150
Plus 4 Adder tadd4 70
Shift-left 2 tshift 10
Sign-extend tsext 15
For each of the following two instructions, what is the total time in ps needed from the moment the clock edge triggers the PC to read the instruction address until the data is ready to be written to its destination (register file or data memory) right before the next clock edge?
Note: This is not the Tcas in the lecture and hence no need to consider the setup time of the register file or the data memory.
i. add $t1, $t2, $t3
ii. sw $t0, 32($s3)