Consider a processor with a direct-mapped write-through cache with 8 blocks each with a double word. Assume that the memory address is 48 bits wide and the memory is byte-addressable. (a) Show the layout of the cache, including the data, valid and tag bits, and any logic required to determine hit/miss and select the appropriate data item when reading from the cache. Also, indicate which bits in the 48-bit memory address are used as block offset (if applicable), byte offset, tag, and index, and show where each of these groups of bits are used in the cache architecture. Make sure to label the width of all fields and signals.
(b) What is the total amount of memory (in bytes) required to build this cache (including both data and other necessary bits)? (show calculations)
(c) What is the block offset (if applicable), byte offset, tag, and index for byte address 56? Give your answer in decimal notation.
(d) What is the block offset (if applicable), byte offset, tag, and index for double-word address 56? Give your answer in decimal notation. Note: A double address refers to the memory address without the byte offset (the most significant 45 bits of the address)
(e) Given the series of double-word addresses: 2, 5, 10, 7, 1, 5, 2, 9, 7, Complete the table below. Assume the cache is initially empty. Label each reference as a hit or a miss and show the final contents of the cache in the diagram you drew under (a). Address Index Tag Hit/Miss 2 5 10 7 1 5 2 9 7 (f) The following miss rate measurements have been made. Instruction miss rate is 6%; data miss rate is 8%. Assume that one-half of the instructions contain a data reference and that the cache miss penalty in no. of clock cycles is (6 + (Block size in double-words)). Calculate the average miss penalty per instruction.