Step 1: Create a combinational RTL model for a 4-bit expandable carry lookahead adder (CLA). You do not need to create or use gate-level modules for full or half adders. A combinational RTL model uses only continuous assignment (assign) statements or always_comb procedural block with or without gate delays.
Use these gate delays in your model:
AND gate 2ns
OR gate 2ns
XOR gate 3ns
Step 2: Create an expandable 8-bit adder using the 4-bit CLA module you created and verified.
Your design modules MUST be declared as follows to be instantiated correctly in the testbench:
module CLA4Bit(ain, bin, cin, sum, cout);
input [3:0] ain, bin;
input cin;
output logic [3:0] sum;
output logic cout;
module CLA8Bit(ain, bin, cin, sum, cout);
input [7:0] ain, bin;
input cin;
output logic [7:0] sum;
output logic cout;