Cache Miss Count: Variable size 1D array sequential access with direct-mapped cache For a 4KB, direct-mapped cache with 16-byte blocks, consider the following code snippet.
#define SIZE 1490
short A[SIZE]; //
short is 2B short total = 0;
for (int i = 0; i < 10; i++){
for (int j = 0; j < SIZE ; j++) {
total += A[j];
}
}
Only array A is stored in memory, and all other variables are register allocated. A is stored starting at address 0x450E000. The cache uses a Least Recently Used replacement policy. Note: The memory is byte addressable as always and data is stored in row-major order. Assume that the cache is initially empty.
(a) Calculate the number of misses for array A.
Number of Misses: number (rtol=0.05, atol=1e-08)
(b) Calculate the number of misses for array A if SIZE = 10990.
Number of Misses: number (rtol=0.05, atol=1e-08)
(c) Calculate the number of misses for array A if SIZE = 3230.
Number of Misses: number (rtol=0.05, atol=1e-08)