We begin with a computer implemented in a single-cycle implementation. When the stages are split by functionality, the stages do not require exactly the same amount of time. The original machine had a clock cycle time of 12 ns. After the stages were split, the measured times were IF, 3 ns; ID, 2.5 ns; EX, 2 ns; MEM, 3 ns; and WB, 1.5 ns. Use 0.1 ns for the pipeline register delay (i. e., the additional time to spend for keeping more registers and logic between pipeline stages). A. What is the clock cycle time of the 5-stage pipelined machine?
B. If there is a stall every 4 instructions, what is the CPI of the new ?machine?
C. What is the speedup of the pipelined machine over the single- cycle machine?
D. If the pipelined machine had an infinite number of stages, what would its speedup be over the single-cycle machine?