Design the pipeline of a new microprocessor. There is an example workload program core with 106 instructions. Each instruction takes 100 ps to finish. a. How long does it take to execute this program core on a nonpipelined processor?
b. The current state-of-the-art microprocessor has about 20 pipeline stages. Assume it is perfectly pipelined. How much speedup will it achieve compared to the nonpipelined processor?
c. Real pipelining isn’t perfect since implementing pipelining introduces some overhead per pipeline stage. Will this overhead affect instruction latency, instruction throughput, or both?