In this exercise we compare the performance of 1-issue and 2-issue processors, taking into account program transformations that can be made to optimize for 2-issue execution. Problems in this exercise refer to the following loop (written in C): for(i=0;i!=j;i+=2)
b[i]=a[i]–a[i+1];
A compiler doing little or no optimization might produce the following LEGv8 assembly code:
MOV X5, XZR
B ENT
TOP: LSL X10, X5, #3
ADD X11, X1, X10
LDUR X12, [X11, #0]
LDUR X13, [X11, #8]
SUB X14, X12, X13
ADD X15, X2, X10
STUR X14, [X15, #0]
ADDI X5, X5, #2
ENT: CMP X5, X6
B. NE TOP
The code above uses the following registers:.
i j a b Temporary values
X5 X6 X1 X2 X10–X15
Assume the two-issue, statically scheduled processor for this exercise has the following properties:
1. One instruction must be a memory operation; the other must be an arithmetic/logic instruction or a branch.
2. The processor has all possible forwarding paths between stages (including paths to the ID stage for branch resolution).
3. The processor has perfect branch prediction.
4. Two instruction may not issue together in a packet if one depends on the other. (See page 345.)
5. If a stall is necessary, both instructions in the issue packet must stall. (See page 345.)
As you complete these exercises, notice how much effort goes into generating code that will produce a near-optimal speedup.
4.31.2 [10] <§4.10> What is the speedup of going from a one-issue to a two-issue processor? (Assume the loop runs thousands of iterations.)