In the cache coherence problems (Question 1 & 2) you can make the following assumptions: • Bus transactions available for address X: ReadReq, WriteReq, WriteBack, ReadResp · Caches respond with data before memory if they have it A) A 3-processor systems implements cache coherence with a snoopy MSI protocol. For each access in the sequence below (to the same address), list the coherence states for each processor's cache after the access and what transactions will appear on the bus. Coherence State P1 P2 1 P3 Action start P1 read Bus Transactions (& comments) - - P1 write P2 read P3 read P1 read P2 write
B) If the system above was upgraded to MESI, would that lead to improvement for the given sequence? If so, would any of those differences help?