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Your L1 data cache has an access latency of 1ns, your L2 cache has an access latency of 10 ns, and main memory has an access latency of 200ns. Assume that 95% of your L1 accesses are hits, 90% of your L2 accesses are hits and that 100% of your main memory accesses are hits. What is the average memory latency as seen by the processor core?

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Your L1 data cache has an access latency of 1ns, your L2 cache has an access latency of 10 ns, and m...

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