The processor needs to compute the next PC after each instruction. Write a verilog module which computes the next PC. Be sure to include the B, and CBZ cases. You may use the output of the "Control" module.

Check the explanation

Explanation:

module calculatePC (

input Rst, // Reset is asynchronous an active high

input [15:0] BranchAddress, // Branch Address

input Clk, // Clock of MPU

input B, // Branch instruction is Recieved

input CNZ, // Compare with Zero and Branch is Recieved

input ZeroFlag, // Zero Flag input

output [19:0] PC // Program Counter

);

reg [19:0] NextPC, PC;

always "at" (*)

begin

if (B == 1'b1)

NextPC = BranchAddress;

else if ((CNZ == 1'b1) && (ZeroFlag == 1'b1))

NextPC = BranchAddress;

else

NextPC = NextPC + 20'd4;

end

always "at"(posedge Clk or posedge Rst)

begin

if (Rst)

PC <= 20'd0;

else  

PC <= NextPC;

end

endmodule