Direct memory access is used for high-speed I/O devices in order to avoid increasing the CPU’s execution load. A. How does the CPU interface with the device to coordinate the transfer? B. How does the CPU know when the memory operations are complete? C. The CPU is allowed to execute other programs while the DMA controller is transferring data. Does this process interfere with the execution of user programs? If so, describe what forms of interference are caused.

Explanation:

a. To initiate a DMA transfer, the CPU first sets up the DMA registers, which contain a pointer  to the source of a transfer, a pointer to the destination of the transfer, and a counter of the number of  bytes to be transferred. Then the DMA controller proceeds to place addresses on the bus to perform transfers, while the CPU is available to accomplish other work.  

 b. Once the entire transfer is finished, the DMA controller interrupts the CPU.  

c. Both the CPU and the DMA controller are bus masters. A problem would be created if both the   CPU and the DMA controller want to access the memory at the same time. Accordingly, the CPU  should be momentarily prevented from accessing main memory when the DMA controller seizes the  memory bus. However, if the CPU is still allowed to access data in its primary and secondary caches,  a coherency issue may be created if both the CPU and the DMA controller update the same memory  locations.  

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