Caches are commonly implemented in SRAM, and the cache layout impacts the total amount of SRAM required to implement the cache. For the following two problems, assume the caches are byte addressable and addresses and data words are both 32 bits. a. How many total bits are required to implement a 128 KiB direct-mapped cache with 4-word blocks? b. How many total bits are required to implement a 128 KiB direct-mapped cache with 32-word blocks?

Answer explained below

Explanation:

1.

The number of bits in cache= 2ⁿ x (block size + tag size + valid field size)

Cache size is 2ⁿ blocks

Block size is 2ᵇ words (2ᵇ+2 words)

Size of tag field 32 – (n + b + 2)

Therefore,

2ⁿ x (2ᵇ x 32 + 32 – (n + b + 2) + 1)

= 2ⁿ x (2ᵇ x 32 + 31 – n - b)

in the given question,

  Cache size = 128 KB = 2¹⁷ bytes = 2¹⁵ words = 2¹³ blocks

Cache entry size = block data bits + tag bits + valid bit

                  = 128 + (32 – 13 – 2 – 2) + 1 = 144 bits

Therefore, cache size = 2¹³' 144 bits = 2¹³' (1.25 ´ 128) bits = 1.25 ´ 2²⁰ bits = 1.25 Mbits

2.

Cache size = 128 KB = 2¹⁷ bytes = 2¹⁵ words = 2¹³ blocks

Cache entry size = block data bits + tag bits + valid bit

                  = 128 + (32 – 10 – 2 – 2) + 1 = 147 bits

Therefore, cache size = 2¹³' 147 bits

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