Elan inserted shapes into a slide in his presentation. what is the quickest way to format those shapes?
o format dialog box
o fill options
o shape styles gallery
o format painter
hurrryy

Some of your friends have gotten into the burgeoning field of time-series data mining, in which one looks for patterns in sequences of events that occur over time. purchases at stock exchanges--what’s being bought-- are one source of data with a natural ordering in time. given a long sequence s of such events, your friends want an efficient way to detect certain "patterns" in them--for example, they may want to know if the four events buy yahoo, buy ebay, buy yahoo, buy oracle occur in this sequence s, in order but not necessarily consecutively. they begin with a collection of possible events (e. g., the possible’ transactions) and a sequence s of n of these events. a given event may occur multiple times in s (e. g., yahoo stock may be bought many times in a single sequence s). we will say that a sequence s’ is a subsequence of s if there is a way to delete certain of the events from s so that the remaining events, in order, are equal to the sequence s’. so, for example, the sequence of four events above is a subsequence of the sequence buy amazon, buy yahoo, buy ebay, buy yahoo, buy yahoo, buy oracle their goal is to be able to dream up short sequences and quickly detect whether they are subsequences of s. so this is the problem they pose to you: give an algorithm that takes two sequences of even~s--s’ of length m and s of length n, each possibly containing an event more than once--and decides in time o(m n) whether s’ is a subsequence of s

Suppose we have a byte addressable computer that has a 32-byte cache with 8 bytes per block. the memory address is 8 bits long. the system accesses memory addresses (in hex) in this exact order: 6e, b9, 17, e0, 4e, 4f, 50, 91, a8, ab, ad, 93, and 94. (a) assuming the cache is direct mapped, what memory addresses will be in cache block 2 after the last address has been accessed? (b) assuming the cache is direct mapped, what is the hit ratio for the entire memory reference sequence given, assuming the cache is initially empty? (c) assuming the cache is 2-way set associative with a lru replacement policy, what is the hit ratio?

Which of the following statements tests if students have a grade of 70 or above, as well as fewer than five absences? a: if(grade > = 70 and daysabsent < = 5): b: if(grade > = 70 or daysabsent < = 5): c: if(grade > 70 and daysabsent < = 5): d: if(grade > 70 or daysabsent < = 5): i took the test the answer is a